This invention relates to semiconductor structures and methods for forming such structures and more particularly to structures having dual damascene recesses formed therein.
As is known in the art, one method for forming interconnects in a semiconductor structure is a so-called dual damascene process. A dual damascene process starts with the deposition of a dielectric layer, typically an oxide layer, disposed over circuitry formed in a single crystal body, for example silicon. The oxide layer is etched to form a trench having a pattern corresponding to a pattern of vias and wires for interconnection of elements of the circuitry. Vias are openings in the oxide through which different layers of the structure are electrically interconnected, and the pattern of the wires is defined by trenches in the oxide. Then, metal is deposited to fill the openings in the oxide layer. Subsequently, excess metal is removed by polishing. The process is repeated as many times as necessary to form the required interconnections. Thus, a dual damascene structure has a trench in an upper portion of a dielectric layer and a via terminating at the bottom of bottom of the trench and passing through a lower portion of the dielectric layer. The structure has a step between the bottom of the trench and a sidewall of the via, at the bottom of the trench.
Two approaches exist for a dual damascene metallization. In the standard approach, i.e., a xe2x80x9cvia firstxe2x80x9d approach, the vias are etched into the oxide first, before the trenches are formed. Both types of openings (i.e., the vias and the trenches) are typically formed by using an anisotropic, or dry etch, such as a reactive ion etch (RIE). A disadvantage of this sequence is that the subsequent trench RIE produces oxide fences at the trench/via interface. These fences have the shape of upright rails. The fences are formed because of the use of an anti-reflective coating (ARC) required for deep ultraviolet (DUV) lithography of trenches with use of polymerizing oxide trench etch. The ARC is necessary to control reflectivity variations caused by the topography from previous processing. The ARC is also required as a protection against RIE attack of underlying films. Since the ARC and photoresist polymers adhere to the bottom of the via opening during the trench lithography step, these polymers act as a mask during the etching of the oxide in the trench formation step, creating fences if the oxide etch is too selective to the ARC. One can also use an oxide etch process with lesser selectivity to polymers, but this leads to critical dimension (CD) loss. The fences are not easily covered by subsequent metallization layers, which causes problems with liner and metal fill instability. Therefore, fences are often responsible for yield degradation in a dual damascene metallization fabricated with the xe2x80x9cvia firstxe2x80x9d approach. More specifically, fences reduce reliability due to electromigration of metal, with early failure of metal lines. This electromigration is induced by metal not completely covering the fences, thereby creating breaks in the metal. Deposition of the metal by chemical vapor deposition (CVD) can prevent these breaks. However, the latter is undesirable because of the expense entailed. As an alternative to photoresist, hard mask lithography/etch can be used for trench definition to avoid fence formation. This is a rather complex process and has its own, unsolved challenges.
In the second approach, i.e. a xe2x80x9ctrench firstxe2x80x9d approach, the trenches are formed before the vias. Here, via lithography is a major challenge, because the vias have to be printed into the topology of the trenches. Reflection from the sidewalls of the trenches makes it difficult to accurately define the vias. Also, the trenches make it difficult to evenly spin on ARC and photoresist. The resist thickness varies, depending on the trench topology. Therefore, the lithographic definition of the vias is done with a non-uniform photoresist thickness, resulting in a very small process window. For optimal planarization of the resist, white space fill is needed. White space fill is a dummy structure whose sole purpose is to improve photoresist thickness uniformity by preventing the photoresist from being thinned too much by being stretched too far between device features. White space fill has the disadvantage of reducing the real estate available for device formation, thereby creating design constraints.
Further, in the xe2x80x9ctrench firstxe2x80x9d approach, ARC cannot readily be used for via definition with a standard lithography scheme. Because ARC provides non-conformal coverage over the corners of the trench, extremely high resist selectivity would be required during the via etch. Failure to obtain high resist selectivity results in critical dimension (CD) loss and device failure. For satisfactory printing of sub-0.5 Tm via patterns without ARC, one needs to use DUV technology with an advanced DUV stepper. An example of such a stepper is the commercially available Micrascan lll (manufactured by Silicon Valley Group, San Jose, Calif. 95110). With this procedure, however, the process window of the via lithography becomes very narrow in terms of DUV parameters. The thickness of the resist varies depending on trench topology. Therefore, across any wafer, there exists a range of optimal focus/exposure conditions. Since only one condition can be chosen, this creates a very small process window, as the focus range for successful via exposure is smaller than that allowed within a manufacturing process. Further, the extendability of the approach to via diameters of less than 250 nm is uncertain, because even with advanced stepper tools, performance of the via lithography is threatened by notching of features or scumming of trenches due to challenges presented by the topology with trenches.
In accordance with the present invention, a method is provided for forming a step in a layer of material. The method includes forming the layer over a substrate. A cavity is formed in a portion of a surface of the layer. The cavity can be either a via or a trench. The formed cavity is filled with a filler material to provide a substantially planar surface over the substrate. The filler material has anti-reflective properties and therefore can also be used for those lithographic processes that require anti-reflective coating prior to photoresist application. A photoresist layer is formed over the substantially planar surface over the substrate. An aperture is formed in the photoresist layer in registration with the formed cavity. The aperture exposes a portion of the filler material. The exposed portion of the filler material is removed along with a contiguous portion of the layer to form the step in the layer. The step has a portion substantially perpendicular to the surface of the layer and a portion substantially parallel to the surface of the layer. The portion substantially parallel to the surface of the layer terminates at a sidewall of the cavity.
In one embodiment of the invention, a trench is formed in a layer of material with a via passing through the layer. The via is disposed at a bottom surface portion of the trench. The method includes forming the layer over a substrate. A first opening is formed in a portion of a surface of the layer. The first opening is filled with a filler material. A photoresist layer is formed over the filler material, filling the first opening, and over a contiguous portion of the surface of the layer. An aperture is formed in the photoresist layer in registration with the formed first opening. The aperture exposes a portion of the filler material. The exposed portion of the filler material is removed along with a contiguous portion of the layer to form a second opening.
In one embodiment the first opening is a trench and the second opening is a via, and in another embodiment the first opening is a via and the second opening is a trench.
In accordance with another embodiment of the invention, a method is provided for forming a trench in a layer of material with a via passing through the layer. The via is disposed at a bottom surface portion of the trench. The method includes forming the layer over a substrate. The via is formed in a portion of a surface of the layer. The formed via is filled with a filler material. A photoresist layer is formed over the filler material and over a contiguous portion of the surface of the layer. An aperture is formed in the photoresist layer in registration with the formed via. The aperture exposes a portion of the filler material. The exposed portion of the filler material and a contiguous portion of the layer are removed to form the trench.
In accordance with still another embodiment of the invention, a method is provided for forming a trench in a layer of material with a via passing through the layer, such via being disposed at a bottom surface portion of the trench. The method includes forming the layer over a substrate. The trench is formed in a portion of a surface of the layer. The formed trench is filled with a filler material. A photoresist layer is formed over the filler material and over a contiguous portion of the surface of the layer. An aperture is formed in the photoresist layer in registration with the formed trench, such aperture exposing a portion of the filler material. The exposed portion of the filler material and contiguous portion of the layer are removed to form the via in a bottom surface portion of the trench.
This process allows a much wider process window for DUV lithography, even on conventional DUV steppers, by expanding the focus/exposure window of exposing vias into topology. The process is extendable to  less than 0.25 Tm. The process requires a DUV resist with a high selectivity to standard polymer etch processes, such as ARC RIE or resist recess. Currently these properties are offered by a variety of multi-layer systems, including CARL (developed by Siemens AG, Munich, Germany, available from Clariant GmbH, AZ Electronic Materials, Wiesbaden, Germany) and ERIS bilayer systems (manufactured by JSR Microelectronics, Sunnyvale, Calif.). These DUV bilayer resist systems have a Si methacrylate top layer and a phenolic-based planarizing bottom layer polymer. Therefore an etch selectivity of resist top layer/bottom layer polymer comparable to that of polysilicon/polymer is expected. For example, using an O2 or SO2 chemistry mentioned below allows one to obtain selectivities of  greater than 20:1.
Further, by using Siemens CARL resist, one eliminates the need for using an ARC, because CARL resist has anti-reflective properties. The use of this filler material provides an advantage over conventional lithography where ARC thickness is typically limited to 1000 xcex94, because one cannot spin the material to a greater thickness. Therefore, conventional ARC materials cannot provide adequate planarization. Thereby, the first layer of the CARL resist provides advantages of both planarization and anti-reflection.